The high level schematic for our board is shown below, there's nothing really surprising here, it's really quite similar to the ideal DC-DC buck converter diagram I showed above.

The schematic is a little messy due to the rushed manner in which it was done, but it covers the basics.

I'll try to cover all the interesting components going forward, if there's something you'd like to understand in more detail feel free to reach out to me at me@OwenBrake.com.

Note: You will notice throughout the schematics there are various net classes I define (TSV, GLV, etc.) these are all spacing net classes to ensure clear seperation between the high voltages and prevent any arcing. Learn more here.

This is probably the real interesting part of the project and one which people care the most about. I did a full analog control topology for this DC-DC converter.

For the inexperienced, a fully analog control topology is basically unheard of in modern industry. If you're designing something yourself there are tons of off-the-shelf ICs that will regulate control for you. If you really want even more control over the dynamics you would do digital control using a microprocessor. I decided to go with analog control for a few reasons.

1. Fully analog control allows me to perform quick reliable simulations on the dynamics of the system without having to worry about complex IC SPICE models. With digital control it's very difficult to get good simulations integrated.

2. Debugging/Integration: If I used some off-the-shelf IC, the chance I will fully understand how it works on a deep level within the timeline is practically impossible. With this fully analog control if there's something wrong with it, I can identify it quite easily as I designed the whole thing. Op-amps have well-defined operating characteristics.

3. Looking at it from a time-efficient manner, having to integrate a microcontroller on the board and then writing firmware, bringing up drivers takes time. It's all pretty simple stuff, but getting something I am going to trust to operate stably at these high-voltages and perhaps manually tuning the PID gains is not something I deemed worth the hassle.

4. It's cool and I wanted to test it out. This might be the best reason, and one that swayed me the most. I like analog electronics, I like control systems. It's very rare that either of these fields are really practical in the real world, now everything is digital and advanced controls is just ML based or guess and checked PID gains. It was a fun project, it worked and I got to apply a whole bunch of different fields to get this result.

Just looking at it, it is quite daunting to take in, but once you break it down it is quite simple. I go into some mathematics in this section. But one thing I've learned in EE design from mentors and especially from the "Art of Electronics" is don't get bogged down in the math. When you're starting out design, think through it logically as blocks, run simulations for some proof and if you have to do deep analysis then bring out the math.

We'll begin as with any system by breaking it down into sub-sections.

The way one typically does DC-DC control is they have a reference waveform ("chopper") and when the reference waveform rises above some threshold it will trigger "on" the MOSFET and when it's below the threshold is turns "off".

I've done this by using an analog triangle wave generator as shown.

One way to think about this, is as 2 different stages of op-amps.

Non-Zero Reference Schmitt Trigger
The first op-amp (U3) is effectively a non-zero reference schmitt trigger, when the input rises above a threshold it drives HIGH, and remains HIGH until it reaches a low threshold in which case it drives LOW. The characteristics equations for this are shown here:

$$\begin{array}{ccc}{V}_{\mathrm{ref}}& =& \mathrm{2.5V}\\ R_1& =& \mathrm{69.8k\Omega }\\ R_2& =& \mathrm{100k\Omega }\\ V_{\mathrm{o+}}& ~& \mathrm{5V}\\ V_{\mathrm{o-}}& ~& \mathrm{0V}\\ V_{TL}& =& \frac{R_1+R_2}{R_2}{V}_{ref}-\frac{R_1}{R_2}{V}_{o-}\\ V_{TH}& =& \frac{R_1+R_2}{R_2}{V}_{ref}+\frac{R_1}{R_2}{V}_{o+}\end{array}$$

The result is you get a LOW threshold of ~0.75V and a HIGH threshold of ~4.25V.

Integrator
The second op-amp (U4) is an inverting integrator. When the input to this stage is greater than 2.5V, the op-amp will integrate in the negative direction. When the input to this stage is less than 2.5V the op-amp will integrate in the positive direction.

The RC combination are selected to set the slope of the integration. This directly sets the switching frequency for the device. The characteristic equation for an inverting op-amp integrator is shown below.

$$V_o=-\frac{1}{RC}{\int }_0^t{V}_{in}dt$$

You can then simplify to get the rate of change of the output voltage which gives you the slope of your triangle wave.

$$\frac{d{V}_o}{dt}=-\frac{1}{RC}(2.5)$$

You can rearrange to do the math and you get the following result for switching frequency.

$$f_{sw}=\frac{2.5}{2RCV}$$

In this case "V" is your peak-peak voltage of your schmidt trigger. In our case it's approximately 3.5 (4.25-0.75), you solve that and you get a switching frequency of ~12kHz. Though due to stage loading and non-idealities in op-amps you should run simulations to get a more accurate result. Our result is really about 10kHz switching frequency, but the exact number is not that important for us.

Combined Stages
When you combine the 2 stages, you get an op-amp which is always integrating it's input. So given a DC voltage from the Schmitt trigger it's creating a linear slope based on that. The Schmitt trigger reads the integrator output and when it reaches a certain threshold it flips it's own output HIGH/LOW. The integrator receives that output and changes direction of it's integration. This creates a perfect triangle wave as the stages are constantly reacting to each other.

This part is pretty simple. Effectively for our regulator, to control our reference we need some concept of input.

This is a dead simple voltage divider, it takes in the output voltage and steps it down such that 300V output ~2.5V in to the op-amp.

The regulator part is perhaps the coolest part.

Resistor Ladder Input
We'll start with the left part. As stated we have the resistor ladder which steps down our measured output voltage from 300V to ~2.5V. This gets buffered and passed into one side of our feedback regulator (U6).

Reference Input
On the other side we have a simple resistor ladder (R25, R33). All this really is, is it sets our reference voltage we want to achieve. As I stated before the input get's scalled from 300V to ~2.5V. Our desired reference voltage is set to be at ~2.5V.

You'll notice there's a MOSFET (Q3) there. It serves a very simple purpose, when ENABLE is low, Q3 enters the cutoff region, which due to the pull-down resistor pulls our reference voltage low, and subsequently our regulator will begin to cutoff.

You'll also notice there's a capacitor (C22) there. This acts as a soft-start, the RC circuit has a time constant of ~0.1s, so in about 0.5s the reference will have reached steady state.

The real complicated bit comes with the main regulator (U6). What is implemented here is a Type II compensator. I don't quite have the time to an in-depth analysis of the stability of the Type II compensator and performing selection of the components. If you're curious TI has a pretty good article here.

Less-Technical Version
This regulator toplogy is trying to minimize the error between it's 2 input terminals. It will try to set it's output such that the input from SENSE_V is equal to the reference voltage divider. We can tune the various component values to get good tradeoffs between stability and response time. If we say increased C3, we would have a slower, more stable response but a longer response time to changes in the system.
Technical Version
The Type II compensator was selected to give stronger control over the transient response while maintaining high stability. There is a pole at the origin to give good steady-state tracking. There's a zero placement at ~2Hz to speed up the transient response, while a pole is placed at ~15kHz to try and dampen out the high frequency noise and switching action. In hindsight, the pole should have probably been placed quite a bit slower to smooth out more of the switching action. I was tuning control loops in simulation very late in the night and was planning on tuning parameters in person at some point.

I've sketched up a quick bode plot as shown below, so you can see the frequency response of the system.

Finally there is the op-amp comparator (U5). This is a very simple comparator that outputs HIGH when the triangle wave output is above the reference voltage set by our Type II compensator (U6). It outputs LOW when the triangle wave output is below said reference voltage. This is effectively triggering the MOSFET for the DC-DC switching action ON and OFF.

We already discussed briefly the enable MOSFET, so I will skip over that for now. You can learn more about it here.

This circuit here is really simple. It simply takes the voltage measurement stepped down from the output voltage. It then buffers it, filters it a bit and sends it through a comparator. In this case, ENABLE_OUT gets driven HIGH if the input voltage is ~1.666V which refers to an output voltage of ~200V.

ENABLE_OUT get's sent through an optocoupler device to isolate the HV referenced electronics. This is then used to trigger ENABLE on the 2nd stage DC-DC. You can get more context in the high-level schematic here.

The over-voltage protection circuit is also quite simple. All it is, is a comparator circuit that triggers HIGH when the sensed input voltage rises above 3.33V which corresponds to an output voltage of ~404V. When it outputs HIGH it drives the MOSFET Q4 gate which pulls acts as a pull-down which turns the regulator OFF as it pulls the reference for the comparator to 0.

The gate driver circuit is really simple. GaN HEMT driving can typically be very tricky and require advanced circuits, but I had no issues during my testing with this topology. I performed very little analysis, I just trusted GaN Systems' writings that you can drive these GaN chips using a standard Si driver (see here for more details).

There's not much to say here it's a very simple topology. Isolated DC-DC module to supply the power for the gate drive unit. 10 ohm resistor is used to slow the rise time of the gate of the FET. This is a GaN FET it has very high rise times, and we don't have a ton of time to do in-depth parasitic inductance analysis so we'll just slow down the rise times and if switching losses become an issue we can tune those later.

Note:I'm going to breeze through inductor and capacitor selection, it's not very interesting.

In sum, for capacitor and inductor selection, you need to ensure you have low output ripple, proper voltage ratings, low mass, low losses and ensuring the system remains in continuous conduction mode.

For the inductor I found a fairly compact and very high inductance inductor (2.2mH) that could still handle the current I hoped for (~2A) (here). I stuck 3 of those in series, while ensuring that I stuck a connector across them so we could add more in the future if that was deemed necessary.

For the input capacitance I selected a 650V 20uF film capacitor (this one).

For the output capacitance I selected 4 450V 10uF aluminum capacitors (these ones).

If you run the calculations from above you end up with a ripple voltage of <1V, which is pretty good for our use case. Should also be noted that the 2nd stage DC-DC itself has a ton of input capacitance which will help shrink our ripple.

I wanted to minimize mass for this design. Setting up a huge heatsink and having to worry about the creepage issues as we'd have to properly ground to the chassis this heatsink was not something I was interested in doing.

What I opted to do was, get a GaN HEMT, this would cost a bit extra but it would save on volume, it would yield very low switching losses while still having fairly low on-state resistance.

The GS65516T has a low RDS(on) of 25mΩ and tiny gate charge of 14.2nC. It also has a VDS(max) of 650V. All in all it works great for our application, at our low switching frequency of 10kHz switching with this should not generate high losses, and at a maximum current of only about 2A you're looking at most 100mW conduction loss.

The plan was to put this under load and see if purely natural convection of this fairly significant thermal pad would yield a fairly decent operating margin. Perhaps we'd have to put a fan near it, or worst case a very tiny heatsink.